ghdl
Open-source simulator for the VHDL language.
- Analyze a VHDL source file and produce an object file:
- Elaborate a design (where `{design}` is the name of a configuration unit, entity unit or architecture unit):
- Run an elaborated design:
- Run an elaborated design and dump output to a waveform file:
- Check the syntax of a VHDL source file:
- Display the help page:
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