6502 Instructions

Based on https://www.masswerk.at/6502/6502_instruction_set.html

Instructions by Name

ADC

add with carry

AND

and (with accumulator)

ASL

arithmetic shift left

BCC

branch on carry clear

BCS

branch on carry set

BEQ

branch on equal (zero set)

BIT

bit test

BMI

branch on minus (negative set)

BNE

branch on not equal (zero clear)

BPL

branch on plus (negative clear)

BRK

break / interrupt

BVC

branch on overflow clear

BVS

branch on overflow set

CLC

clear carry

CLD

clear decimal

CLI

clear interrupt disable

CLV

clear overflow

CMP

compare (with accumulator)

CPX

compare with X

CPY

compare with Y

DEC

decrement

DEX

decrement X

DEY

decrement Y

EOR

exclusive or (with accumulator)

INC

increment

INX

increment X

INY

increment Y

JMP

jump

JSR

jump subroutine

LDA

load accumulator

LDX

load X

LDY

load Y

LSR

logical shift right

NOP

no operation

ORA

or with accumulator

PHA

push accumulator

PHP

push processor status (SR)

PLA

pull accumulator

PLP

pull processor status (SR)

ROL

rotate left

ROR

rotate right

RTI

return from interrupt

RTS

return from subroutine

SBC

subtract with carry

SEC

set carry

SED

set decimal

SEI

set interrupt disable

STA

store accumulator

STX

store X

STY

store Y

TAX

transfer accumulator to X

TAY

transfer accumulator to Y

TSX

transfer stack pointer to X

TXA

transfer X to accumulator

TXS

transfer X to stack pointer

TYA

transfer Y to accumulator

Instructions by Category

Load & Transfer Instructions

Load, store, interregister transfer.

Stack Instructions

These instructions transfer the accumulator or status register (flags) to and from the stack. The processor stack is a last-in-first-out (LIFO) stack of 256 bytes length, implemented at addresses $0100 - $01FF. The stack grows down as new values are pushed onto it with the current insertion point maintained in the stack pointer register.

(When a byte is pushed onto the stack, it will be stored in the address indicated by the value currently in the stack pointer, which will be then decremented by 1. Conversely, when a value is pulled from the stack, the stack pointer is incremented. The stack pointer is accessible by the TSX and TXS instructions.)

Increment & Decrement

Arithmetic Operations

Logical Operations

Shift & Rotate Operations

All shift and rotate instructions preserve the bit shifted out in the carry flag.

Flag Instructions

Comparison Instructions

Generally, comparison instructions subtract the operand from the given register without affecting that register. Flags are still set as with a normal subtraction and thus the relation of the two values becomes accessible by the Zero, Carry and Negative flags.

(See the branch instructions below for how to evaluate flags.)

Bit Testing Operations

The BIT instruction is somewhat similar to the CMP instruction, but performs a bit-wise comparison between the contents of the accumulator and a memory location given as the operand.

BIT performs a logical AND operation between the two values and sets the Zero flag according to the result. Additionally, bit #7 (sign-bit) and bit #6 of the operand are transferred to the respective bits of the status register, the Negative flag and the oVerflow flag. (Thus, these two bits can be easily used to store and set flags for conditional branches, see below.)

The contents of the accumulator remains uneffected.

Conditional Branching Instructions

Branch targets are relative, signed 8-bit address offsets.

(An offset of zero corresponds to the immedately following address. While it is perfectly feasible to calculate offsets by hand, more often these are computed by an assembler program from absoulte addresses or labels. In the latter case, branch instructions may look more like absolute address mode instructions, while taking in actuality just a relative offset as a single-byte operand.)

Jump Instructions

JSR and RTS affect the stack as the return address is pushed onto or pulled from the stack, respectively.

(JSR will first push the high-byte of the return address [PC+2] onto the stack, then the low-byte. The stack will then contain, seen from the bottom or from the most recently added byte, [PC+2]-L [PC+2]-H.)

Interrupt Instructions

A hardware interrupt (maskable IRQ and non-maskable NMI), will cause the processor to put first the address currently in the program counter onto the stack (in HB-LB order), followed by the value of the status register. (The stack will now contain, seen from the bottom or from the most recently added byte, SR PC-L PC-H with the stack pointer pointing to the address below the stored contents of status register.) Then, the processor will divert its control flow to the address provided in the two word-size interrupt vectors at $FFFA (IRQ) and $FFFE (NMI).

A set interrupt disable flag will inhibit the execution of an IRQ, but not of a NMI, which will be executed anyways.

The break instruction (BRK) behaves like a NMI, but will push the value of PC+2 onto the stack to be used as the return address. Also, as with any software initiated transfer of the status register to the stack, the break flag will be found set on the respective value pushed onto the stack. Then, control is transferred to the address in the NMI-vector at $FFFE.

In any way, the interrupt disable flag is set to inhibit any further IRQ as control is transferred to the interrupt handler specified by the respective interrupt vector.

The RTI instruction restores the status register from the stack and behaves otherwise like the JSR instruction. (The break flag is always ignored as the status is read from the stack, as it isn't a real processor flag anyway.)